This invention relates to DRAM devices. More particularly, the present invention is directed to DRAM devices employing open digit line array architecture.
As is well known in the art and shown in FIG. 1, a DRAM cell 100 typically comprise a capacitor 104 and access transistor 108 pair. One plate of the capacitor 104 is connected to a common cell plate (not shown) to which all capacitors in that DRAM cell array are connected, a subset of which is shown in FIG. 1. The other plate of the capacitor 104 is coupled to a drain of the access transistor 108. The gate of the access transistor 108 is connected to a word line 116 which allows all the DRAM cells coupled to each word line 116 to be activated, while the source of the access transistor 108 is coupled to a digit line 120 which the DRAM cell 100 will read from and write to during memory operations. Activating the gate of the access transistor allows a high voltage charge (Vcc) or low voltage charge (ground) carried by the digit line 120 to pass to the capacitor 104, thus writing the voltage of the digit line 120 to the capacitor 104.
DRAM cell storage technology of this type is understandably transitory in nature: the high or low voltage charge written to the capacitor will eventually dissipate, as charges stored across capacitors are known to do. As also is known in the art, stored charges leak across the dielectric core between the transistor plates, and voltages can leak from the plates through the access transistors to which they are connected. As a result, the contents of DRAM cells typically must be refreshed hundreds of times per second.
A network of sense amplifiers 124 (FIG. 1) typically are used to refresh the contents of the DRAM cells, each of the sense amplifiers 124 comparing voltages received on pairs of digit lines 120 to which each is connected.
The memory cells 100 are shown in FIG. 1 arranged in an open digit line configuration in which each sense amplifier 124 is coupled to a column of memory cells in one array 125 and another column of memory cells in another memory array 126. Each pair of digit lines 120 to which each sense amplifier 124 is connected comprises an active digit line and a reference digit line. The active digit line 128 is the digit line in one array 125 to which the access transistors 108 of the DRAM cells 100 being refreshed are coupled upon activation of the word lines 116 activating the gates of the access transistors 108. The active digit line is assumed to be the top digit line 128 in the array 125 for purposes of the example of FIG. 1. The reference digit line 132 is a digit line connected to a row of DRAM cells 100 whose contents will not be refreshed during the refresh cycle and is assumed to be the digit line 132 in the array 126 for purposes of the example of FIG. 1. Prior to the refresh cycle, both the active digit line 128 and reference digit lines 132 are equilibrated by precharging the digit lines 120 to Vcc/2 so that the sense amplifiers 124 can measure the voltage disparity between them.
When the access transistors 108 of the DRAM cells 100 coupled to the active digit line 132 and the sense amplifiers 124 are activated, each of the sense amplifiers 124 determines which of the two digit lines 120 carries the higher voltage and the lower voltage, and then drives the higher voltage digit line toward Vcc and the lower voltage digit line toward ground. Thus, when the row of DRAM cells 100 coupled to the active digit line 128 is activated, each of these DRAM cells 100 storing a high voltage charge, even allowing for leakage which necessitates these refresh cycles, should carry a voltage of something greater than Vcc/2. Similarly, DRAM cells 100 storing a low voltage charge, allowing for leakage, should carry a voltage of less than Vcc/2. Ideally, therefore, the sense amplifiers drive the DRAM cell 100 coupled to each of the active digit lines toward Vcc or ground, whichever voltage was stored in the DRAM cell 100 before it was refreshed.
However, conditions are not always ideal. For example, depending upon the combinations of charges stored in the DRAM cells 100 coupled to the active digit lines 128, the sense amplifiers 124 might not accurately read the charges on the DRAM cells 100 coupled to the active digit lines 124. For example, if a capacitor 104 of a DRAM cells 100 stores a high voltage charge, but, for some reason, the voltage read by the sense amplifier 124 appears to be below the equilibrated Vcc/2 value of the reference digit line 132, the sense amplifier 124 will drive the active digit line 132 toward ground, refreshing the previously high voltage charge carrying DRAM cell to 100 a low voltage state, corrupting data
One way this can happen is through voltage fluctuations or noise affecting digit lines to which a sense amplifier 124 is coupled. More specifically, since the active digit line 128 extends though one array 125 and the reference digit line 132 extends through a different array 126, the active digit line 128 and the reference digit lines 132 can be exposed to different noise sources. Noise signals coupled to one of the digit lines 128 or 132 but not the other 132 or 128 can cause the sense amplifiers 124 to sense an erroneous voltage level. The manner in which noise signals can be coupled to the active digit line 128 and the reference digit line 132 will be discussed in greater detail below.
As mentioned earlier, differential noise coupled to the digit lines 128, 132 is a problem with the open digit line architecture shown in FIG. 1 primarily because the active digit line 128 and the reference digit line 132 extend through different arrays 125, 126, respectively. In contrast, an array 250 having a folded digit line architecture shown in FIG. 2A does not have this problem. The folded digit line array 250 includes a sense amplifier 262 coupled to respective complimentary pairs of digit lines 258 provided for each column 266 of memory cells 254. Each digit line 258 is connected to alternate memory cells 254 in each column 266. For each read or write operation, one of the digit lines 258 in each pair serves as the active digit line and the other digit line 258 in the pair serves as the reference digit line. Thus, instead of extending through different arrays as in an open digit line architecture, active and reference digit lines 258 having a folded architecture extend through the same array 250 in close proximity with each other. As a result, arrays 250 having a folded digit line architecture have good common mode noise rejection since the active and reference digit lines 258 are exposed to the same noise sources to substantially the same degree.
Although a folded digit line architecture provided good common mode noise immunity, it has the disadvantage of consuming more area on a semiconductor die (not shown) compared to an open digit line architecture, which is shown in FIG. 2B. As is well known in the art, each memory cell in an open digit line architecture requires only 4F2 or 6F2 in area, where F represents the feature size, whereas each memory cell 254 in a folded digit line architecture requires 8F2 in area. This significant disparity allows memory devices using an open digit line architecture to consume substantially less space on a semiconductor die so that such memory device can be substantially cheaper than memory devices using a folded digit line architecture.
FIG. 2B shows two open digit line sub-arrays 200 and 202. Digit lines 203, 204 connected to each sense amplifier 206 in the open digit line sub-arrays 200 and 202 are not connected to memory cells 208 in the same sub-array. Instead, each sense amplifier 206 is connected to one digit line 203 in one sub-array 200 and one digit line 204 in a second sub-array 202. Each sub-array 200, 202 has its own cell plate 210, 212, respectively coupled to the memory cell capacitors in its respective sub-array 200, 202. Furthermore, each sub-array 200, 202 is often fabricated in separate semiconductor wells that form separate substrates 214, 215 that are isolated from each other, such as by using a xe2x80x9ctriple wellxe2x80x9d structure, which is known in the art. As will be appreciated, the digit lines 203 in the first sub-array 200 can be exposed to difference noise sources than the noise sources to which the digit lines 204 in the second sub-array are exposed. Noise can be coupled to the digit lines 203, 204 differently for several reasons. For example, because the digit lines 203, 204 in the different sub-arrays 200, 202 are fabricated in different substrates, noise signals generated in the substrates can be coupled to the digit lines 203, 204. Differential noise can also result from noise signals coupled to differently to the cell plates 210, 212 in each sub-array 200, 202, respectively.
Various approaches have been used to improve the noise immunity of memory devices using an open digit line architecture. One approach has been to couple corresponding nodes in the sub-arrays 200, 202 to each other so that a voltage disturbance or noise in one of the nodes will also occur in the corresponding node. As a result, if the voltage disturbance or noise is coupled from the node to a digit line in one array, the voltage disturbance will, in theory, also be coupled from the corresponding node to the corresponding digit line in the other array. For example, as shown in FIG. 2B, the cell plate 210 of the first sub-array 200 and the cell plate 212 of the second sub-array 202 are electrically connected by a conductive coupling 217. Theoretically, this measure should alleviate uneven cell plate disturbances by bringing all the coupled cell plates to the same voltage. Similarly, a conductor 219 is used to couple the substrate 214 in which one sub-array 200 is fabricated to the substrate 215 in which the other array 202 is fabricated. Although these conductive couplings 217, 219, as well as other conductors (not shown) coupling corresponding nodes to each other, do, in fact, improve the noise immunity of the sub-arrays 200, 202 in some cases, they can actually creates noise problems that have very adverse consequences, as will be explained below.
With further reference to FIG. 2B, assume that one of the memory cell capacitors 216 in the sub-array 200 is storing a high voltage, e.g., VCC, and all of the other memory cell capacitors in the sub-array 200 are storing a low voltage, e.g. ground potential. This is known as a xe2x80x9c1 in a sea of zerosxe2x80x9d situation. The capacitor 216 and all of the other capacitors in the sub-array 200 are coupled to the same cell plate 210. As previously explained, the digit lines 203 in the sub-array 200 are equilibrated to one-half the supply voltage, i.e., VCC/2, prior to a memory read operation. Assuming that the sub-array 200 is an active array, when the access transistors 203 are activated for the memory cells 208 storing a 0, the voltage on each of the capacitor plates in such memory cells quickly transition from 0 volts to the equilibrated voltage VCC/2 of the digit lines. The sudden increase in voltage coupled to all of the memory cell capacitors except for the capacitor 216 causes the voltage of the cell plate 210 to also increase. The voltage increase on the cell plate 210 is also coupled to the memory cell capacitor 216, which has a plate that has been charged to VCC.
The cell plate 210 is also coupled to the capacitor 104 of the lone cell 216 storing a 1. As a result, the cell plate 210 will tend to drive the voltage stored in the capacitor 216 higher as well. This makes it more likely that the sense amplifier 206 will correctly sense the voltage on the capacitor 216 as corresponding to a 1. However, because the cell plate 210 of the sub-array 200 is also coupled to the cell plate 212 of the array 202, the voltage on the cell plate 212 also increases. This increase in voltage of the cell plate 212 can be capacitively coupled to the reference digit line 204 in the array 202. In fact, the voltage disturbance on the cell plate 210 can be coupled to the reference digit line 204 with an even greater magnitude than it is coupled to the active digit line 203, partly because any voltage increase in the active digit line 203 is coupled to the capacitor 216, which somewhat acts as a low-pass filter. Thus, the conductor 217 provided to couple the cell plates 210, 212 to each other for the purpose of reducing data read errors, can actually increase data read errors. Similarly, the conductor 219 coupling of the substrates 214, 215 for the sub-arrays 200, 202, respectively, to each other can also increase rather than decrease memory read errors.
In an open digit line array architecture device, the types of cell plate and semiconductor substrate disturbances previously described could be overcome by refreshing the memory cells more often. After all, if memory cells were refreshed before the voltages they stored dissipated so as to closely approach Vcc/2, the type of voltage disturbances previously discussed would no longer pose a problem. On the other hand, refreshing memory cells consumes appreciable amounts of power, and it is desirable to reduce power consumption in memory devices to avoid generation of waste heat and, more importantly, to help prolong battery life in portable devices.
There is therefore a need for a circuit and method that can obtain the size advantages of an open digit line architecture without incurring the power consumption costs typically incurred by the higher refresh rates needed for memory devices using an open digit line architecture.
The present invention is directed to a system and method for selectively coupling and decoupling sub-arrays in open digit line array memory devices to prevent cell plate and semiconductor substrate disturbances from causing memory cell read and refresh errors. In particular, the present invention exploits the fact that, when the memory cells in a sub-array store an appreciably unbalanced number of either zeroes or ones, the nominal voltages of the cell plate and/or substrate for the sub-array undergo transient changes that can result in data read errors. More specifically, in an open digit line architecture, the present invention couples cell plates and/or substrates to the cell plates and/or substrates, respectively, between adjacent arrays to allow for the equalization of cell plate and/or substrate voltages up until the equilibrated active digit lines are to be coupled to the memory cells to read and/or refreshed the memory cells. The cell plate and/or substrate for the active sub-array are then decoupled from the cell plate and/or substrate of the reference sub-arrays to reduce the coupling of any voltage transient in the cell plate and/or substrate of the active sub-array to the cell plate and/or substrate of the reference sub-arrays.